Memory devices are typically provided as internal, semiconductor, integrated circuits in apparatuses such as computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile (e.g., flash) memory.
In a continuing process of forming ever increasing number of memory cells on an integrated circuit, memory manufacturers have begun fabrication of three-dimensional (3D) memory formed using semiconductor pillars. Some 3D vertical memory architectures include polysilicon channels that can introduce several deleterious effects relative to a planar memory equivalent.
For example, bulk traps/defects in the polysilicon channel of vertical memory architectures can give rise to relatively large reverse-biased junction leakage and gate-induced drain leakage (GIDL) currents. The same junctions in the vertical memory architecture typically provide low reverse biased off-state leakage under some bias conditions. These junctions can also act as current supplies to provide high junction leakage for other array operations that use similar bias conditions. This conflicting requirement can result in limiting the operating margin memory array operations (e.g. erase, program, read).
Thus, there are conflicting specifications for vertical memory architecture that can impose a series of fundamental engineering trade-offs. There are general needs to improve operating margins while reducing GIDL current.